1. Technical Field
The present invention relates to the field of computer software and, more particularly, to methods of transferring data between bus devices.
2. Description of Related Art
On a multi-processor bus with a split response protocol, the first phase of the response indicates successful receipt of the bus transaction and the device that is the target of the transaction. The second and final phase of the response is when the attached bus devices report the cache-coherency state of the target address.
When different types of devices are attached to the same bus (i.e. compute processors along with I/O processors), the set of bus transactions supported is usually the least common denominator of all of the attached devices. This often results in higher-performance transaction types being disabled in a system because of a single lower-performance device on the bus that does not support those transactions. The potential performance loss is magnified when the low-performance device is accessed infrequently (i.e. the majority of transactions are between devices which all support the higher performance transaction types but which must be disabled).
Therefore, there is a need for a mechanism where higher-performance transaction types can be supported within a system containing different types of devices, even though not all devices on the bus support those transaction types.
The present invention provides a method of transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data to other devices in the computer system. The computer-system identifies, from a plurality of responding devices within the computer system, a target device that contains the data. In response to a determination that the target device does not support higher-performance transactions, the computer system disables higher-performance transactions and transfers the data to the requesting device via a lower-performance transaction process.